Design of multipliers for GF(2 m )
Zhi‐Hong Mao, Guochu Shou, Youbing Hu, Zhongyong Guo · Electronics Letters · 2010
A new design of multipliers for GF(2m) based on combination of bit-serial and bit-parallel schemes with low complexity is proposed. Using pipeline architecture, the scheme yields significantly lower latency compared to known bit-parallel multipliers for GF(2m).