SOC HW/SW co-verification technology for application of FPGA test and diagnosis
A.W. Ruan, Yuxin Wang, K. Shi, Zixuan Zhu, Qiong Wu, Xiuyou Han, Yulong Liao · 2011 International Conference on Computational Problem-Solving (ICCP) · 2011
Process of configuration and fault scan is required to be repeated many times before all resources of a FPGA-under-test are tested and diagnosed. Both FPGA test system and test schemes have been studied and presented in the keynote. Construction of the in-house developed FPGA test system is based on SOC HW/SW co-verification technology. Algorithms for FPGA test and diagnosis covering all FPGA resources such as, configurable logic blocks (CLBs), interconnect resources (IRs), input/output blocks (IOBs), wide edge decoder, et al with minimum configuration numbers are also discussed. Not only multiple faults in FPGA can be detected, but location and type of the multiple faults can also be determined by the FPGA test system and associated test schemes. Furthermore, 100% fault coverage can be achieved in experiment.