Asynchronous circuit synthesis: persistency and complete state coding constraints in signal transition graphs
Ruchir Puri, Jun Hua Gu · International Journal of Electronics · 1993
The synthesis of asynchronous circuits is a challenging problem in VLSI design. Event based specification such as signal transition graphs are simple and powerful in specifying and synthesizing asynchronous behaviour. In this paper, the relation between signal transition graph syntactic constraints, i.e. persistency and complete state coding, is considered. A direct proof of the conditions under which a persistency violation leads to a complete state coding violation is presented. These conditions establish a direct correspondence between two syntactic constraints.