Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs
Katherine Shu-Min Li, Yi-Yu Liao · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2012
An interconnect-driven layout-aware multiple scan tree (MST) synthesis methodology for 3-D integrated circuits (ICs) is proposed. MSTs, also known as scan forest, greatly reduce test data volume and test application time in system-on-a-chip testing. Previous studies on layout-aware scan tree synthesis only address 2-D layouts, so they cannot be directly applied to 3-D ICs. The proposed algorithm effectively optimizes both test compression rate and routing length under 3-D IC-induced constraints, and produces better results than all previous known methods.