High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS
Jae-sun Seo, Ron Ho, Jon K. Lexau, Michael Dayringer, Dennis Sylvester, David T. Blaauw · 2010
We present circuits for efficient repeaterless on-chip wires. A transmitter sends RZ pulses to a clockless hysteresis receiver using a 3-tap FIR filter to control ISI. Partly overlapped bits double bandwidth using adaptive pre-emphasis. A 90 nm CMOS testchip shows bandwidth density of 4.4 Gb/s/¿m over 5 mm on-chip links with 0.34 pJ/b energy consumption.