Real Time Head Detection for Embedded Vision Modules
Alfredo Gardel, Ignácio Bravo, Pedro Gil-Jiménez, Lazaro J.L, A Torquemada · 2007
This paper shows the algorithm implementation for a FPGA based design for people counting using a low level head detection method. Different annular patterns are used to process in parallel the image and detect heads of different sizes. Preprocessing and edge extraction are also made using reconfigurable hardware. The developed system exploits hardware processing as the vision algorithm has been modified and tuned for hardware implementation using almost the 100% of area resources of a Spartan3 (1.5 Mgates) and performing in real time with similar results than other more sophisticated algorithms while using very low cost circuits.