High-level synthesis of fault-secure microarchitectures
Ramesh Karri, Alex Orailoğlu · 1993
Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip.A consequent increase in the number of on-chip faults as well as the growing import of quality metrics such as reliability and fault-tolerance are necessitating on-chip fault-tolerance.On-chip realization of a computation is fault-secure if no fault in the computation goes undetected.In this paper, we present high-level synthesis of fattlt-secure microarchitectures which require less than proportional increase in hardware.The proposed strategy selects intermediate computations for additional voting.The resulting class of fanltsecure microarchitectures supplants the enormous hardware requirements of naive fault-secure strategies with enhanced hardware utilization afforded bysecuring the intermediate computations.1 Introduction Shrinking device dimensions and low operating voltages have rendered VLSI systems susceptible to faults [12], thereby mandating on-chip fault-tolerance.Nevertheless, design of fault-tolerant ICS is not only complex but entails both an area overhead, and a performance penalty.Fault-tolerance becomes manageable at higher levels of design abstraction while preserving the numerous design options in terms of area us performance trade-offs.Fault-tolerance in general refers to a collection of techniques to mask/detect/recover-from/diagnose faults.Depending on the target environment a particular technique becomes appropriate.For example, systems used in Iife-criticaf applications cannot tolerate any faulty results.Consequently, it is crucial to detect alf faults in a timely fashion.Faultsecurity is a technique that can detect all faults in a sys- tem and it can be done online.A computation on a set of processors is fault-secure if no faultl in the computation (generated by a faulty processor) goes undetected.A microarchitecture can be secured against faults by straightforward duplication and voting.Since the hardware overhead of such a naive fault-securing strategy is enormous, we propose synthesis of alternate, low cost, fault-secure