Assertion-based power/performance analysis of network processor architectures
Jia Yu, Wei Wu, X. Chen, Harry Hsieh, Jun Yang, Felice Balarin · 2004
Network processors (NPUs) have emerged as successful platforms to provide both high performance and flexibility in building powerful routers. With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in NPU development. In this paper, we present an assertion-based methodology for system-level power/performance analysis of network processor designs, which can help designers choose the right architecture features and low power techniques. We write power and performance assertions, based on logic of constraints. Trace checkers and simulation monitors are automatically generated to analyze the power and performance characteristics of the network processor model. Furthermore, we apply a low power technique, dynamic voltage scaling (DVS), to the network processor model, and explore their pros and cons with the assertion-based analysis technique. We demonstrate that the assertion-based methodology is useful and effective for system level power/performance analysis.