On cacheability of lock-variables in tightly coupled multiprocessor systems
Reinder J. Bril · ACM SIGARCH Computer Architecture News · 1987
This paper presents a discussion of the cacheability of lock variables in tightly coupled multiprocessor systems with private cache memories. It shows that lock operations can give rise to a problem even when the requirement for a memory scheme to be coherent is met. This problem is called the lock consistency problem .Several solutions are presented to overcome this problem using standard instructions like test-and-set, and optionally a dedicated unlock (or reset) instruction meant to be used for lock-variables exclusively. The feasibility of these solutions depends on the kind of the interconnection network used (i.e., circuit switching or packet switching) and on how a cache memory may get exclusiveness of a block containing a lock-variable.Finally, it Is shown that the lock consistency problem may be solved independently from the cache consistency problem by distinguishing between lock-blocks and non-lock-blocks, facilitating a separation of concerns.