A systolic power-sum circuit for GF(2/sup m/)
Shyue‐Win Wei · IEEE Transactions on Computers · 1994
A systolic power-sum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). This new circuit is constructed by m/sup 2/ identical cells, each of which consists of three 2-input AND logical gates, one 2-input XOR gate, one 3-input XOR gate, and ten latches. The AB/sup 2/+C computation is required in decoding many error-correcting codes. The paper shows that a decoder implemented using the new power-sum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional product-sum multipliers.>