Optical and electronic error correction schemes for highly parallel access memories
Mark Allen Neifeld, Jerry D. Hayes · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1993
We have fabricated and tested an optically addressed, parallel electronic Reed-Solomon decoder for use with parallel access optical memories. A comparison with various serial implementations has demonstrated that for many instances of code block size and error correction capability, the parallel approach is superior from the perspectives of VLSI layout area and decoding latency. The demonstrated Reed-Solomon parallel pipeline decoder operates on 60 bit input words and has been demonstrated at a clock rate of 5 MHz yielding a demonstrated data rate of 300 Mbps.