Data-folded architecture for running 3-D DWT using 4-tap Daubechies filters
Bijit Kumar Das, Swati Banerjee · IEE Proceedings - Circuits Devices and Systems · 2005
A real-time 3-D sub-band coding (SBC) technique using a discrete wavelet transform is proposed. The main advantages of the proposed scheme lie in the reduction of wait time and diminution of buffer size in 3-D SBC. The major delay which is due to the group of frames (GOF) generation in the temporal direction is decreased by dynamic updating of the transform coefficients. The dynamic updating handles much a lower dimension of data compared to 3-D SBC, and thus facilitates better hardware utilisation with lower overhead. A data-folding architecture is used in unison with the CORDIC-based QMF lattice filters for realisation of 2-D DWTs using a 4-tap Daubechies filter. The data scanning pattern for the spatial domain signal results in a low-complexity control circuit. The multiplierless DWT architecture operating at 100 MHz is implemented on 0.25 μm BiCMOS technology and found to have much lower power dissipation compared to the multiplier-based structures for FIR realisation. The optimised design of the DWT filter using data-folding architecture resulted in an appreciable low memory budget of N2/4+2N for 2-D DWT and O(N2/M) time required for temporal direction decomposition. Hardware utilisation in the proposed architecture is 100%.