VAST: Virtually Associative Sector Translation for MLC Storage Systems
Jen-Wei Hsieh, Yu-Cheng Zheng, Yong-Sheng Peng, Po-Hung Yeh · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2013
In recent years, multilevel cell Flash memory (MLC), which stores two or more bits per cell, has gradually replaced single-level cell flash memory due to its lower cost and higher density. However, MLC also brings new constraints, i.e., no partial programming and sequential page writes within a block, to the management. This paper proposes a virtual log-block-based hybrid-mapping scheme, referred to as virtually associative sector translation (VAST), for MLC storage systems. Unlike traditional hybrid-mapping schemes, VAST is a combination of block-level and segment-level mappings and manages log blocks in a flexible manner. The goals of our research are to avoid timeout by decreasing dummy-page writes, to get a better response time by decreasing live-page copies, and to prolong the life span of flash memory by decreasing total block erasures. Our trace-driven simulation shows that VAST could reduce up to 90% of dummy-page writes, 22%~52% of live-page copies, and 55%~83% of block erasures, compared to well-known hybrid-mapping schemes.