DVFS-enabled sustainable wireless NoC architecture
Jacob Murray, Partha Pratim Pande, Behrooz Shirazi · 2012
In the design of high-performance massive multi-core chips, power and heat have become dominant constraints. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance and increase cooling costs. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links and DVFS-enabled wireline links facilitate design of energy and thermally efficient and hence sustainable multi-core chips. Our performance analysis demonstrates that the DVFS-enabled Wireless NoC improves overall energy dissipation by around 60% and reduces the temperature of the hottest node in the network by up to 30% depending on the specific application without incurring any latency penalty over a traditional mesh network.