A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
Chiu-Wing Sham, Xu Chen, Francis C. M. Lau, Yue Zhao, Wai M. Tam · IEEE Transactions on Circuits and Systems I Regular Papers · 2013
This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10-13at a bit-energy-to-noise power-spectral-density ratio (Eb/N0) of 3.55 dB.