FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification
Murad Qasaimeh, Assim A. Sagahyroon, Tamer Shanableh · IEEE Transactions on Computational Imaging · 2015
This paper proposes a parallel hardware architecture for real-time image classification based on scale-invariant feature transform (SIFT), bag of features (BoFs), and support vector machine (SVM) algorithms. The proposed architecture exploits different forms of parallelism in these algorithms in order to accelerate their execution to achieve real-time performance. Different techniques have been used to parallelize the execution and reduce the hardware resource utilization of the computationally intensive steps in these algorithms. The architecture takes a 640 × 480 pixel image as an input and classifies it based on its content within 33 ms. A prototype of the proposed architecture is implemented on an FPGA platform and evaluated using two benchmark datasets: 1) Caltech-256 and 2) the Belgium Traffic Sign datasets. The architecture is able to detect up to 1270 SIFT features per frame with an increment of 380 extra features from the best recent implementation. We were able to speedup the feature extraction algorithm when compared to an equivalent software implementation by 54× and for classification algorithm by 6×, while maintaining the difference in classification accuracy within 3%. The hardware resources utilized by our architecture were also less than those used by other existing solutions.