Simulating the behaviour of software modules by trace rewriting
Yabo Wang, David Lorge Parnas · International Conference on Software Engineering · 1993
The trace assertion method is a module interface specification method based on the finite state machine model. To support this method, the authors plan to develop a specification simulation tool, a trace simulator, that symbolically interprets trace assertions of trace specifications and simulates the externally observable behavior of the modules specified. They first present the trace assertion method. Then trace rewriting systems are formally defined, and it is shown that trace rewriting, a technique similar to term rewriting, can be applied to implement trace simulation. >