A Hiererachical, Error-Tolerant Compactor
C. Kingsley · Design Automation Conference · 1984
This paper describes a compactor that is practical for compacting whole chips that are designed hierarchically, and can produce a reasonable result in spite of the layout being over-constrained. The layout produced is good enough to be used in high volume chips. The compactor is currently used in a cell layout system and a chip assembly tool.