Evaluating a system based design flow
Thorsten Schubert, Jens-E. Appell, Wolfgang H. Nebel, J. Hanisch, Joachim Gerlach · Electronic Systems and Software · 2004
It takes a number of languages and re-implementation steps to turn an architecture into a design. A refinement-based systemic flow could reduce the effort with no loss in silicon efficiency. One team decided to find out whether that was the case. Different domains such as analogue hardware, digital hardware and software each have their specialised languages and tools. Even when restricting to a single domain like digital hardware, still a diversity of languages and tools is used. For example, Matlab is very popular for algorithmic modelling, especially in the signal processing community. C and C++ are often used for similar purposes when high simulation performance is required. For the actual implementation of hardware, register-transfer level (RTL) modelling with VHDL and Verilog is predominant. Language changes between the different stages of the design process require manual recoding, which is laborious and error-prone. Furthermore, language changes in the design flow complicate the verification of the design. Either a co-simulation between the different languages has to be done, or the testbench has to be rewritten in the new language. SystemC promises to overcome this problem by providing a single modelling framework that covers a wide range of abstraction levels.