BIST POWER MINIMIZATION BY TRANSITION REDUCTION – A REVIEW
Akash Sao, Arya Mohan · International Journal of Modelling and Simulation · 2009
The widespread use of battery-powered CMOS–VLSI devices inportable communication and computing equipments necessitatedshift in the emphasis of designing built-in self-test (BIST) for VLSIfrom high fault coverage to low power dissipation during test mode.