Structural BIST insertion using behavioral test analysis
Mehrdad Nourani, C. Papachristou · 1997
The purpose of this work is to develop a test synthesis technique based on BIST methodology which uses the test metrics (i.e. controllability and observability) obtained by test analysis of the behavior to enhance the testability quality (fault coverage) of the corresponding structure and obtain the scheduled test behavior accordingly. The key feature of this work is in using the Structured Data Flow Graph (SDG) which annotates the behavioral information (e.g. data dependency) and structural information (e.g. binding, connectivity). To enhance testability of the structure, the SDG will be modified using transformation technique to improve the fault coverage and shorten the test schedule. 1. Introduction The design complexity of microelectronic chips continues to increase. Testing of these complex chips is becoming prohibitively expensive in regards to equipment and time. There are a great number of alternative test methodologies such as built-in self testing (BIST), which can be perf...