A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL
Konstantinos Vitoroulis, Tadeusz Obuchowicz, Asim J. Al-Khalili · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2007
In this paper we present a CAD tool capable of generating a variety of parallel prefix adders described in the VHDL language. The VHDL code generated by the tool is synthesizable and the resulting adders can be used as design components in an automatic or semi-custom design flow. In its current version the tool is able to generate arbitrary bit-size prefix adders of the following types: Sklansky, Ladner-Fischer, Kogge-Stone, Han-Carlson, Brent-Kung and Knowles.