An alterable programmable logic array
J. F. P. Marchand · IEEE Journal of Solid-State Circuits · 1985
The NMOS alterable programmable logic array (APLA) performs the same logical function as a standard programmable logic array, but it can be programmed and reprogrammed electrically to change the logic function. Each term in the AND and OR array of the APLA can be individually enabled or disabled by writing a memory cell associated with it. The prototype array has 22 inputs, 22 outputs, and 64 product terms. The chip can be programmed through a standard microprocessor interface. The performance, operation, and layout of the PLA array; the basic dynamic memory cells; and the methods used to load and refresh the memory are described.