PGA-STC: programmable gate array for implementing self-timed circuits
KAPILAN MAHESWARAN VENKATESH AKELLA · International Journal of Electronics · 1998
This paper describes a new FPGA architecture called PGA-STC (programmable gate array for implementing self-timed circuits). PGA-STC differs from Montage (Hauck et al. 1994) in using a programmable delay element to implement both data and control sections of asynchronous systems efficiently and without hazards. Implementation of macromodule-style self-timed circuits with bundled-data communication in PGA-STC is discussed. Details of the architecture and the technology mapping are presented with illustrative examples.