A self-tuning hybrid flash translation layer for embedded systems
Radoslav Mladenov, Sava Ivanov · 2011
The paper represents an approach for designing and implementing a hybrid variant of a flash translation layer. The two classic realizations are the page-mapping FTL and the block-mapping FTL. The page-mapping FTL keeps an address table referring each page of the flash memory array, which is very flexible but takes much space in the RAM because it keeps a descriptor for each page. The block-mapping FTL on the other hand keeps an address table of the blocks which takes far less space but its effectiveness is degraded because of the lack of proper addressing scheme and that's why it is not used frequently. In this paper we will expose an algorithm which in a way combines the two classic approaches and thus mitigates the negative impact of the straightforward solutions.