A FASTBUS Processor Interface Using a 68000 Microprocessor
Y. Arai, T. Murakami, E. Inoue, Yukio Karita, I. Endo, Fumio Shimokoshi · IEEE Transactions on Nuclear Science · 1984
A versatile FASTBUS master utilize a 68000 microprocessor has been developed. The module implements geographical, logical and broadcast addressing and is able to handle the FASTBUS Service Request. The data transfer rate is about 800 kB/sec by using window driver. The logics and test results are described.