Architectures for 3780 point FFT processor
Jing He, Li Tianyue, Xinyu Xu · 2011
3780 point FFT processor is the key component in DTMB receiver. It is generally implemented by decomposing 3780 point to small size, which can be implemented with WFTA and PFA in pipelined architecture. Several architectures were proposed and patented, the differences of the architectures lie in the way 3780 are decomposed and the processing order of small sized WFTA module. In this paper, the architectures for 3780 point FFT processor are analyzed, and the architectures with different processing order and internal wordlength are modeled with Matlab and simulated, the simulation results shows that processing larger sized WFTA at first stages can achieve better performance, and the varied decomposition and processing order can achieve varied performance in terms of SQNR and hardware cost.