Power and Area Efficiency NoC Router Design for Application-Specific SoC by Using Buffer Merging and Resource Sharing
Kun-Lin Tsai, Hao-Tse Chen, Yo-An Lin · ACM Transactions on Design Automation of Electronic Systems · 2014
Network-on-Chip (NoC) is an efficient on-chip communication architecture specifically for System-on-a-Chip (SoC) design. However, the input buffers of a NoC router often take a significant portion of the silicon area and power consumption. Besides, the performance of a NoC is also greatly affected by the buffer size. In this article, a static buffer merging and resource sharing method is proposed for the application-specific SoC minimizing the NoC buffer. When given an application-specific task graph and the dataflow distribution, the proposed method statically merges rarely used buffers and generates the suitable number of input buffers for each router at design timely. The merged buffer is shared by several input directions. The experimental result shows that the buffer can be utilized more effectively after the resource sharing. Based on the synthesized design with TSMC 90nm technology, the proposed method reduces an average of 42.23% area and 35.13% power while providing similar performance.