Hardware design of the scalable video encoder for the multi-source digital home environment
Zong-Hong Li, Hsueh-Yi Lin, Tsung‐Han Tsai · 2012
In this paper, hardware realization of the scalable video compressor encoder is proposed to achieve the requirement of the multi-source digital home environment. The Proposed 2-D DWT architecture is composed of two 1-D DWT and internal buffer. Moreover, the parallel scanning method is realized to reduce the internal buffer size instead of the conventional line-based scanning method. On the other hand, a pipelined MQ encoder architecture is also proposed to increase the throughput. After the synthesis, the throughput of proposed hardware realization is 93.3M samples/sec by adopting 0.18 μm CMOS technology. The power dissipation is 48.22 mW under 100 MHz clock source. The throughput meets the requirement of real-time processing of a 720p/30 fps video sequence, demanded by the digital home environment.