Enhanced superscalar hardware
J. K. Pickett, D. G. Meyer · 1993
In the push for ever increasing performance out of processor architectures, there is a need to expand bqond the limitations of existing scalar approaches.Superscalar architectures provide one such means.By dynamically executing more than one instruction per clock cycle, superscalar architectures can improve performance without relying solely on technology improvements for these gains.lhis paper examines a new technique for superscalar control implementation, called the schedule table.i'he schedule table facilitates dependency checking, out of order instruction issue, out of order execution, branch prediction, speculative execution, precise interrupts, and fmt and eficient misprediction recovery.