On-chip interconnection network for accelerator-rich architectures
Jason Cong, Michael Gill, Yuchen Hao, Glenn Reinman, Bo Yuan · 2015
Modern processors have included hardware accelerators to provide high computation capability and low energy consumption. With specific hardware implementation, accelerators can improve performance and reduce energy consumption by orders of magnitude compared to general purpose cores. However, hardware accelerators cannot tolerate memory and communication latency through extensive multi-threading; this increases the demand for efficient memory interface and network-on-chip (NoC) designs.