A 2 K byte fully-associative cache memory with on-chip DRAM control
Steve Griffith, S. Golson · 1989
A 2 kbyte cache memory with on-chip DRAM (dynamic random-access memory) control has been built. The fully-associative write-back write-allocate cache is organized as 128 lines by 16 bytes. The part directly connects to and controls an array of 1 Mb DRAMs forming a 4 Mbyte parity-checked memory subsystem. Zero-wait-state operation of the Intel 80386 microprocessor at 25 MHz is supported. Fabricated in a 2 μm CMOS process, the 374-mil×383-mil die contains 172 K transistors