Logic design of decoded-programmable logic arrays
YONG-XIN XIAO · International Journal of Electronics · 1990
Decoded-programmable logic arrays (D-PLAs) consist of three parts: the D array, the AND array and the OR array. They have a distinct advantage over ordinary PLAs in that they occupy smaller areas than ordinary PLAs for realizing the same functions. This paper considers some basic problems in the design of D-PLAs. A tabular method is proposed for the minimization of OR–AND–OR expression of boolean functions, which can deduce minimizing OR–AND–OR expressions from the usual AND–OR expression. The procedure can easily be implemented as a computer program, and it is not essential for the designer to generate all the prime implicants or list all the minterms. The complexity of the assignment of the input variables will also be discussed.