Bit-level arithmetic optimization for carry-save additions
Kei-Yong Khoo, Zhan Yu, Alan N. Willson · 1999
Abstract—This paper addresses the bit-level optimization of carry-save adder (CSA) arrays when the operands are of unequal wordlength (such as in some datapaths in digital sig-nal processing circuits). We first show that by relaxing the carry-save representation to allow for more than two signals per bit position, we gain flexibility in the bit-level imple-mentation of CSA arrays that can be exploited to achieve a more efficient design. We then propose algorithms to opti-mize a single adder array at the bit-level. In addition, we proposed a heuristic to optimize a series of adder arrays that might occur in a datapath. We have applied our algorithms to the optimization of high-speed digital FIR filters and have achieved 15 % to 30 % savings (weighted cost) in the over-all filter implementation array in comparison to the standard carry-save implementation. I.