On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator
Mei Wen, Nan Wu, Chunyuan Zhang, Qianming Yang, Jun Ren, Yi He, Wei Wu, Jun Chai, Maolin Guan, Changqing Xun · IEEE Micro · 2008
In this paper shows the extension of application domains, hardware-managed memory structures such as caches are drawing attention for dealing with irregular stream applications. However, since a real application usually has both regular and irregular stream characteristics, conventional stream register files, caches, or combinations thereof have shortcomings. This article focuses on combining software- and hardware-managed memory structures and presents a new syncretic memory system based on the ft64 stream accelerator.