Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
Nicola Bombieri, Franco Fummi, Graziano Pravadelli · ACM Transactions on Design Automation of Electronic Systems · 2008
In transaction-level modeling (TLM), verification methodologies based on transactions allow testbenches, properties, and IP cores in mixed TL-RTL designs to be reused. However, no papers in the literature analyze the effectiveness of transaction-based verification (TBV) in comparison to the more traditional RTL approach. The first contribution of this article is the introduction of a functional-fault-model-based methodology for demonstrating the effectiveness of reuse through TBV. A second contribution is the introduction of a similar methodology for efficient property checking which identifies and removes redundant properties prior to assertion-based verification or model checking.