A computer controlled tester for logic networks and a method for synthesizing test patterns

K.J. Crook, J. Blythin · Radio and Electronic Engineer · 1970

This paper describes a total test system for logic networks as manufactured for digital electronic equipment. The system provides a means of physically testing the manufactured item together with a method for preparing test data automatically using a computer. The method uses sensitive path techniques with forward and reverse simulation of a software model of the network which is held in the computer store. The justification for automatic test synthesis lies in the large number of network types which are designed.

Read the paper · More papers on PaperTik