IDDQtest vector selection for transistor short fault testing
Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita · Systems and Computers in Japan · 1997
IDDQ testing is indispensable in improving the quality of CMOS circuits. Currently, IDDQ testing is usually conducted by using IDDQ test vectors selected from a test set generated for logic testing. Since IDDQ measurement is relatively slow, it is necessary to select a set of IDDQ test vectors which is as small as possible and which can detect as many faults as possible. In this paper, we consider the problem of IDDQ test vector selection based on the transistor short fault model. First, we define fault equivalence for the transistor short-fault model and propose methods for reducing the number of faults that need to be considered by equivalence fault collapsing. Then, we formalize the IDDQ test vector selection problem and propose a new selection method based on fault tables. Furthermore, we show the effectiveness of the proposed method by experimental results. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(5), 11–21, 1997