A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations
Kazutoshi Kobayashi, Kazuya Katsuki, M. KOTANI, Yuta Sugihara, Y. KUME, H. ONODERA · IEICE Transactions on Electronics · 2007
We have fabricated a LUT-based FPGA device with functionalities measuring within-die variations in a 90 nm process. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Random variations are dominant in a 48 x 48 configurable array laid out in a 3 mm x 3 mm square region. It has a functionality to measure delays on actual signal paths between flip flops by providing two clock pulses. Measured variations are used to maximize the operating frequency of each device by choosing the optimal paths. Optimizations of routing paths using a simple model circuit reveals that performance of the circuit is enhanced by 2.88% in average and a maximum of 9.34%.