An Experimental 50-Megacycle Arithmetic Unit
R. M. Walker, D. E. Rosenheim, Peter A. Lewis, A. G. Anderson · IBM Journal of Research and Development · 1957
An experimental 50-megacycle arithmetic unit has been built which performs a repetitive multiplication program and checks the results for errors. The unit uses pulse circuitry which has been developed to perform digital operations at a 50-megacycle pulse-repetition rate. This paper describes the arithmetic system and the circuits which perform the required functions. These circuits include a full binary adder, a phase-locked frequency divider which provides a 3.125-megacycle secondary timing source, a reshaping and retiming circuit using germanium diodes and capacitive storage, a high-speed shift register, a high-speed indicator register, and a binary word generator.