An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems
Chen-Hsing Wang, Chieh-Lin Chuang, Cheng‐Wen Wu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009
This paper presents a highly efficient multimode multiplier supporting prime field, namely, polynomial field, and matrix–vector multiplications based on an asymmetric word-based Montgomery multiplication (MM) algorithm. The proposed multimode 128$\times$32 b multiplier provides throughput rates of 441 and 511 Mb/s for 256-b operands over$GF(P)$and$GF(2^n)$at a clock rate of 100 MHz, respectively. With 21 930 additional gates for Advanced Encryption Standard (AES), the multiplier is extended to provide 1.28-, 1.06-, and 0.91-Gb/s throughput rates for 128-, 192-, and 256-b keys, respectively. The comparison result shows that the proposed integration architecture outperforms others in terms of performance and efficiency for both AES and MM that is essential in most public-key cryptosystems.