Parallel architecture for prototype training
M. Zhu, N.K. Loh, S. Khalaf, Pepe Siy · Electronics Letters · 1986
The letter suggests an efficient parallel hardware architecture for prototype training in pattern recognition. Sample means and covariance matrices are computed by the same architecture and much attention is paid to the implementation of covariance matrices. A k2-chip of processor elements is used to implement covariance matrices.