Automatic verification of asynchronous circuits
T.W.S. Lee, Mark R. Greenstreet, C.-J.H. Seger · IEEE Design & Test of Computers · 1995
Verifying asynchronous designs is difficult, since design errors may manifest themselves only under rare circumstances. This article describes how to model asynchronous designs as programs in synchronized transitions, a general-purpose hardware description language. The authors show how this representation facilitates rigorous, efficient verification.>