Multi-histogram ADC BIST System for ADC Linearity Testing
Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong · 2013
This paper describes an ADC BIST system that utilizes a modified linear ramp histogram approach to test the linearity of an ADC with 10 bits of resolution on a System-On-Chip (SoC). The system tests the differential non-linearity (DNL) and Integral Non-linearity (INL) of an ADC. The ADC is tested in sections using a small amplitude triangle wave which is generated by charging and discharging an on-chip capacitor. This is an alternative solution to test an ADC when ADC-DAC loopback testing is not feasible. Both the ADC and BIST are designed in the 40 nm process node. Simulation results show that the BIST is capable of testing a 10-bit ADC.