Fast square root architecture based on prediction of result bits
MUKESH SHARMA†, Meghanad D. Wagh · International Journal of Electronics · 1992
A new architecture for the fast evaluation of the square-root of normalized binary numbers is presented. It exploits the fact that depending upon the relative magnitudes of the partial result and the partial remainder at any stage of a non-restoring square-root algorithm, a large number of result bits can be predicted. This allows one to convert approximately two thirds of the additions in the square-root procedure to shifts at the cost of a marginal increase in the hardware.