FPGA-based parallel implementation for the lifting discrete wavelet transform
Nazeeh Aranki, Wenqing Jiang, Antonio Ortega · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2000
The rapidly increasing popularity of the discrete wavelet transform (DWT) as an effective tool in many signal processing and data compression applications, and its integration into JPEG 2000 has given rise to various DWT algorithms and their VLSI implementations to reduce complexity and enhance performance. In this paper, we present an efficient hardware implementation of the discrete wavelet transform and its deployment on a reconfigurable FPGA based platform. Our implementation is a novel architecture based on the lifting factorization of the wavelet filter banks. This factorization leads to a block based parallel DWT architecture suitable for hardware implementation. To overcome the communication overhead associated with the DWT block transform, we utilize the new Overlap-State1,2 technique to compute the DWT near block boundaries. A VHDL description of the lifting polyphase factorization architecture was developed and ported to an FPGA hardware platform that was chosen to allow partial and full reconfigurability to accommodate various applications with different filter banks. Our hardware implementation improves the performance by better than twofold speed up when compared to an efficient pipelined FPGA based implementation.