Parallel controller design and synthesis
Matej Jurikovič, Pavel Čičák, Katarína Jelemenská · 2010
Petri nets provide an adequate means to visualize both sequential and parallel controller behavior. They can be used to model and visualize behavior comprising concurrency and synchronization. Strongly time dependent complex controllers can be modeled using Petri nets by introducing several extensions to the basic formalism. The contribution of the work lies in a novel type of Petri net specification, suitable for control unit design. This Petri net is a kind of Synchronous Interpreted Petri net, extended by multi-layer hierarchy and time dependencies. Moreover, a method of the Petri net transformation into synthesizable VHDL code is proposed. The capabilities of the approach are shown by means of a small example illustrating the Petri net creation and its transformation into VHDL behavioral description. The VHDL code synthesizability is demonstrated by synthesis into Spartans 3E FPGA Family and CoolRunner XPLA3 CPLDs Family.