A 2 1/2 -dimensional systolic array architecture
Stephen P. S. Lam · 2002
This paper presents a novel 2 1/2 -dimensional systolic array architecture. The novel systolic array has a logical three-dimensional communication network, but it can be realized on a two-dimensional wafer surface by making use of multiple-layer metalization or multiple chip module technology. The architectural details are discussed in terms of graph theory. Based on several case study, the computational efficiency and hardware overheads for the proposed array are summarised with respect to conventional systolic arrays.>