AC product defect level and yield loss
Jacob Savir · IEEE Transactions on Semiconductor Manufacturing · 1990
The AC defect level and yield loss after test for both logic and random-access memory (RAM) semiconductor chips is considered. Computation of chip AC defect level and yield loss, after test, is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the test error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. The tester accuracy and the test coverage in computing the AC defect level and yield loss are taken into account.>