Low Power Schedule Algorithm for Embedded Multimedia Applications Basing on Imagine-L Processor
Shan Cecilia Cao, Zhaolin Li, Zhixiang Chen, Guoyue Jiang, Shaojun Wei · 2012
The increasing high performance requirement of multimedia applications makes stream processors widely used for multimedia processing acceleration due to the powerful computation. Low power then becomes a critical challenge confronted by stream processors, especially in embedded and realtime situations. In this paper, a low power scheduling algorithm for embedded multimedia applications is proposed, and the H.264 encoding with intra-frame luma prediction is illustrated to demonstrate the schedule efficiency. As the fundamental of the scheduling algorithm, a multi-issued low power processor (Imagine-L) is first introduced which enables both DVFS, DPM techniques and multi-task parallelism. Then, a scheme which contains task mapping, V/F scaling and shutdown assignment is proposed for low power schedule. Task dependency, record dependency, task computation intensity and shutdown breakeven point are all considered in the proposed algorithm to reduce power dissipation. For experimentation a power model is built for Imagine-L processor. The H.264 encoding application is implemented by the proposed algorithm, where 66% power consumption is reduced compared with the Imagine processor.